SPONSORED PROJECTS UNDERTAKEN

 

(a) Thrust Area project:  Establishment of VLSI Design Lab, during 1999-2002 for Rs. 6.00 lac from MHRD New Delhi. 

Coordinator: Dr. Rajeevan Chandel

(b) MODROB PROJECTS:

 

i). Modernisation of Electronic Simulation Lab, Rs. 5.00 Lac, 1999-2002.

      

     Co-Coordinator: Dr. Rajeevan Chandel

 

ii) Establishment of Printed Circuit Board lab, Rs. 8.00 lac during 1999-2001 

iii) Modernisation of Measurement & Instrumentation Lab, Rs. 8.00 lac.

 

 (c) Project: Urban Poverty Alleviation Programme, MUD, Govt. of India, Rs 1.5 Lacs, 2006. 

  Coordinator: Dr. Rajeevan Chandel

(d) VLSI SMDP-II PROJECT FROM DEPARTMENT OF INFORMATION TECHNOLOGY, MIT Govt. of India

This department has received a project on “Special Manpower Development Programme for VLSI Design & related software (SMDP-II)” for a period of 5 years from the Department of Information Technology, Ministry of Communication and Information Technology, Govt.of India, New Delhi in 2006. It is an important and prestigious project through which quality manpower in the area of VLSI Design and related software is planned to be created.

Coordinator:               Dr. Rajeevan Chandel

Co-Coordinator:           Dr. Lalit Awasthi

 

PUBLICATIONS IN INTERNATIONAL / NATIONAL JOURNALS

  1. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “Delay and Power Management of Voltage-Scaled Repeaters for Long Interconnects,” International Journal of Modelling & Simulation, ACTA Press, Canada. http://www.actapress.com. Paper # 205-4356, vol. 27, no. 4, pp. 333-339, 2007.

  2. Rajeevan Chandel, S. Sarkar, and Ashwani Chandel, “Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects”,
    Journal of Low Power Electronics, USA. http://www.aspbs.com, vol. 3, no. 3, pp. 337–344, 2007.

  3. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “An Analysis of Interconnect Delay Minimization by Low-Voltage Repeater Insertion,” Microelectronics Journal, Elsevier Science, Vol. 38, No. 4-5, pp 649-655, April-May 2007.

  4. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “Repeater stage timing analysis for VLSI resistive interconnects”, Microelectronics International-An International Journal, Emerald UK, Vol. 23, No. 3, pp. 19-25, 2006.

  5. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “Repeater insertion in global interconnects in VLSI circuits,” Microelectronics International, Emerald Pub. UK, Vol. 22, No. 1, pp. 43-50, Jan 2005. Website: http://www.emeraldinsight.org.

  6. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “Performance Controlling Parameters of Voltage-Scaled Repeaters for Long Interconnections,” IETE Journal of Research, Vol. 51, No. 2, pp. 107-113, March-April 2005. Website: http://www.iete.org

  7. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “Delay Analysis of a Single Voltage-Scaled-Repeater driven Long Interconnect,” Microelectronics International-An International Journal, UK, Vol. 22,  No. 3, pp. 28-33, 2005. 

  8. Rajeevan Chandel, S. Sarkar and R.P. Agarwal, “Transition Time Considerations in Voltage-Scaled Repeaters,” Microelectronics International, Vol. 22, No. 3, pp.39-40, 2005.  

  9. Rajeevan Chandel and Ashwani Kumar, “Design and Development of Dielectric based Electrostatic Microactuators”, IETE Journal of Research, Vol.46, No. 4, pp. 261-264, July-August 2000.

  10. Rajeevan Chandel and Ashwani Chandel, “SPICE for Nano-regime VLSI Design–A Simulation Study”, IETE Journal of Education, Vol. 48, Nos. 3-4, pp. 103-114, July-December 2007.

  11. Rajeevan Chandel, “Design Techniques for VLSI and Communication DTVC-2007”, VSI Vision, http://vlsi-india.org/ vsi/activities/events.html, vol. 3, no. 2, pp. 25, August 2007.

  12. Rajeevan Chandel, “Study of Voltage-scaled Repeaters for Long Interconnects in VLSI Circuits”, Ph.D. Thesis submitted to IIT Roorkee, July 2005.

  13. Rajeevan Chandel, “VLSI Microfabrication Technologies and MEMS”, IETE Journal of Education, Vol. 42, Nos. 1-4, pp. 33-41, January-December 2001.

  14. Rajeevan Chandel, “Electrostatic Microactuators Using Direct Wafer Bonding Technology”, M.Tech. Dissertation submitted to IIT Delhi, December, 1997.

  15. AKumar, Rajeevan Chandel and J.S. Saini, “Enhancement of Placement Activities in Remotely Located Technical Institutes”, ISTE Journal of Education, Vol. 17, No. 3, pp. 32-36, July-September, 1994.

  16. Vinod Kapoor Bit-Rate Distance Product Enhancement by Compensating Higher Order Dispersion Terms" Ajay K.Sharma, R.K.Sinha, R.S.Kaler, Sandeep Arya & Vinod Kapoor published in the Journal of the Institution of Engineers (I),Vol.83, July, 2002, pp 25-31.

  17. Vinod Kapoor "Non-linear Cross talk in Dispersive SCM-WDM Optical Communication Systems"  Vinod Kumar, Ajay K. Sharma & R. A. Agarwala. has been published in the Journal of the I.E.(India), Volume 85, Jan, 2005, pp 42-44.

  18. "Non linear Cross Talk in PCM Optical Communication Systems" Vinod Kumar, Ajay K.   Sharma & R. A. Agarwala. has been published in the I.E.T.E. (India) Journal of Research, Vol.51, No.2, Mar-Apr, 2005, pp 101-105.

  19. Ashwani Kumar, S.Dasgupta, “Unified Compact Modeling of a gate Tunneling Current considering Image Force Induced Barrier Lowering for a nanoscale N-MOSFET,” Journal of Computational and Theoretical Nanoscience (CTN) Vol 4, No 3,pp 482-487,2007.

  20. Ashwani Kumar, S.Dasgupta, “Analytic Modeling of Non-Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunneling Current for N-MOSFET in Nanoscale Regime.” Journal of Computational and Theoretical Nanoscience (CTN), Vol 4, No 1,pp179-185, 2007.